Freescale Semiconductor /MKV44F16 /SIM /MISCTRL1

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Interpret as MISCTRL1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SYNCXBARAPITTRIG0 0 (0)SYNCXBARAPITTRIG1 0 (0)SYNCXBARAPITTRIG2 0 (0)SYNCXBARAPITTRIG3 0 (0)SYNCXBARBPITTRIG0 0 (0)SYNCXBARBPITTRIG1 0 (0)SYNCDACHWTRIG 0 (0)SYNCEWMIN 0 (0)SYNCCMP0SAMPLEWIN 0 (0)SYNCCMP1SAMPLEWIN 0 (0)SYNCCMP2SAMPLEWIN 0 (0)SYNCCMP3SAMPLEWIN

SYNCXBARAPITTRIG0=0, SYNCXBARAPITTRIG1=0, SYNCXBARBPITTRIG1=0, SYNCCMP3SAMPLEWIN=0, SYNCCMP1SAMPLEWIN=0, SYNCXBARBPITTRIG0=0, SYNCXBARAPITTRIG3=0, SYNCCMP2SAMPLEWIN=0, SYNCDACHWTRIG=0, SYNCCMP0SAMPLEWIN=0, SYNCXBARAPITTRIG2=0, SYNCEWMIN=0

Description

Miscellaneous Control Register 1

Fields

SYNCXBARAPITTRIG0

Synchronize XBARA’s Input PIT Trigger 0 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCXBARAPITTRIG1

Synchronize XBARA’s Input PIT Trigger 1 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCXBARAPITTRIG2

Synchronize XBARA’s Input PIT Trigger 2 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCXBARAPITTRIG3

Synchronize XBARA’s Input PIT Trigger 3 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCXBARBPITTRIG0

Synchronize XBARB’s Input PIT Trigger 0 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCXBARBPITTRIG1

Synchronize XBARB’s Input PIT Trigger 1 with fast clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCDACHWTRIG

Synchronize XBARA’s output for DAC Hardware Trigger with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCEWMIN

Synchronize XBARA’s output for EWM’s ewm_in with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCCMP0SAMPLEWIN

Synchronize XBARA’s output for CMP0’s Sample/Window Input with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCCMP1SAMPLEWIN

Synchronize XBARA’s output for CMP1’s Sample/Window Input with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCCMP2SAMPLEWIN

Synchronize XBARA’s output for CMP2’s Sample/Window Input with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

SYNCCMP3SAMPLEWIN

Synchronize XBARA’s output for CMP3’s Sample/Window Input with flash/slow clock

0 (0): Disable, bypass synchronizer.

1 (1): Enable.

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